By Norman Bonnett (auth.)
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Extra resources for Digital Electronics Through Worked Examples
These are the conditions to CLEAR the flip-flop. a Line 3 of the table shows that when both PRESET and CLEAR are LOW at the same time, then both the outputs from the flip-flop are HIGH. •• J OR N PACKAGE SN74LS76A ••• D, J OR N PACKAGE ITOPVIEWI 1K 10 10 GND 2K 20 20 2J 1J vee 2eLK 2 PRE 2 eLR '71 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K a L H X X X H L H L X X X L H a L L X X X Hf Hf H H J\. J\. J\. J\. l L Oo Co H L H l l H l H H H H H H H H H TOGGLE 'LS76A FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K a l H X X X H L H l X X X L H L L X X X Hf Hf H H I l L ao H Co H I H l H L H H I l H L H H H I H H H H H X X 0 TOGGLE ao Co t This conf•gurattOn tS nonstable; that IS, it will not persist when etther preset or clear returns to its inacttve (high) level.
This is obtained by using master-slave J-Ks. As the input for QC is derived from AND-ing the outputs from A and 8, it can only toggle when QA = 08 = 1 is present at the output of the AND gate before the clock pulse occurs; this occurs when the count goes from 3 to 4. Similarly, the input for D is derived from AND-ing the outputs of A, 8 and C, and so it can only toggle when A = 8 = C = 1, this occurring when the count goes from 15 to 16. 9. 9 Mod-16 synchronous counter, truth table Basic Digital Theory 23 To produce a synchronous BCD counter requires the counter to be reset to 0 when the count changes from 9 to 10; this needs the outputs of B and D to be NAND-ed together and the output of the NAND gate applied to the CLEAR input of all the master-slave J-K flip-flops.
The register is now ready to receive data, so that as data arrives it will be clocked into the register. ) It will require the positive-going edge from four clock pulses to load the data word into the register. On completion of the loading of the fourth bit the data is available for reading from the outputs QA-QD. These 46 Digital Electronics outputs would normally be isolated from the device requesting this data by either a LATCH or a BUFFER. The decision whether or not to use buffers is not normally reached until the specification for the device that gives or takes the data to or from the register has been consulted.