Analog Circuit Design: Smart Data Converters, Filters on by Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

By Michiel Steyaert, Herman Casier, Arthur H. M. van Roermund

Analog Circuit layout comprises the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and invaluable layout rules within the quarter of analog circuit layout. each one half is gifted by way of six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 18 during this winning sequence of Analog Circuit layout, offering priceless info and ideal overviews of: shrewdpermanent information Converters: Chaired by way of Prof. Arthur van Roermund, Eindhoven collage of know-how, Filters on Chip: Chaired through Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired via Prof. M. Steyaert, Catholic college Leuven, Analog Circuit layout is a necessary reference resource for analog circuit designers and researchers wishing to maintain abreast with the most recent improvement within the box. the educational assurance additionally makes it appropriate to be used in a complicated layout.

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Extra resources for Analog Circuit Design: Smart Data Converters, Filters on Chip, Multimode Transmitters

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In the design of [13]. e. 589 bits. 5-bit” in literature [4]. A third option is to allow the stage to extend the full-scale range of the quantizer that takes the over-ranging residue voltage [14]. With proper redundancy in place, large comparator offsets can be tolerated, often allowing the designer to employ basic dynamic latch comparators without preamplification (unless charge kick-back is a concern). Typically, the power required for such comparators in modern technologies is on the order of 100 W/GHz (100 fJ per comparison) or less [15, 16].

This can be seen from Fig. 1, which plots experimental ADC data presented at the IEEE International Solid-State Circuits Conference (ISSCC) and the VLSI Circuit Symposium from 1997 until 2011 [5]. For the range of 50–80 dB signalto-noise-and-distortion ratio (SNDR), the pipelined architecture clearly dominates B. edu M. Steyaert et al. V. 2012 19 20 B. Murmann Flash Folding Two-Step Pipeline (Interleaved) Pipeline (1 Channel) SAR ΔΣ Other 100 fsrm s Jitter 1010 BW [Hz] 109 108 107 106 20 30 40 50 60 70 80 90 100 110 120 SNDR [dB] Fig.

Like most switched capacitor circuits, the stage operates in two main clock phases. During the sampling phase (¥1 ), the stage input signal is acquired. In the redistribution phase (¥2 ), a residual charge packet, controlled by the local conversion result D, is redistributed onto the feedback capacitor CF to produce the amplified stage residue, Vres . In this scheme, the precise matching of capacitors in modern technologies and electronic feedback are leveraged to achieve an accurate realization of the required sub-DAC, subtraction and gain functions.

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